Shallow trench isolation (STI) is widely adopted in an integrated circuit (IC) to provide electrical isolation between adjacent semiconductor devices formed in a substrate. In a CMOS IC, STIs are typically formed between like kinds of NMOS or PMOS transistors in a given well or substrate to suppress leakage current between neighboring devices. These are generally referred to as intra-well isolations. STIs may also be formed between NMOS and PMOS transistors formed in separate wells. STIs thus formed are generally referred to as inter-well isolations and are typically used to suppress leakage current between neighboring devices of opposite-type and/or to prevent CMOS latchup from happening, which typically causes device failure.
FIG. 1 shows a cross-sectional view of a semiconductor device, where prior art STIs 3 are used to isolate MOS transistors formed in semiconductor substrate 2. A P-well and an N-well are formed in a twin-well CMOS manufacturing process. NMOS and PMOS transistors 10 and 20 are then formed in the P-well and N-well, respectively, having source/drain regions and gate regions of 10s, 10d, 10g, and 20s, 20d, 20g. STIs 3 are formed to separate n+ region 10d of NMOS transistor 10 and p+ region 20d of PMOS transistor 20. STIs 3 are also created to separate n+ region 10s and an adjacent n+ region 5 in the P-well, p+ region 20s and an adjacent p+ region 25 in the N-well, respectively. Typically, forming STI 3 involves creating shallow trench into semiconductor substrate 2 through an anisotropic etch process, filling the trench with a dielectric material, such as CVD silicon oxide (SiO2), and removing the excess dielectric using a planarization process, such as chemical mechanic polishing (CMP). In general, the inter-well STI isolation spacing (i.e., n+-to-p+) is substantially wider than the minimum intra-well STI isolation spacing (i.e., n+-to-n+ or p+-to-p+) in order to provide desired isolation effects. This general principle is schematically illustrated in FIG. 1.
However, as the trend of integrating more and more circuit functions in a single IC continues, the structure of existing STIs is gradually becoming one of the major bottlenecks for the further device feature size scaling in advanced technology. Furthermore, a simple feature size shrinkage on an existing STI can lead to deteriorated isolation characteristics and poor device performance. One drawback or challenge related to the structure of a conventional STI 3 in advanced processing technology is that a shrunken inter-well STI typically reduces the n+-to-N-well and p+-to-P-well spacing. When this spacing gets too small, the threshold voltage to turn on the channel regions of the parasitic field device along the side walls of an STI will become very low. Hence, leakage current may substantially increase along the P-well-to-STI, and N-well-to-STI interfaces. Additional detrimental effects include lateral punchthrough in the parasitic device and latchup in the CMOS circuits. Although conventional remedies, such as an increased well dopant concentration and a precisely controlled well doping profile, may be employed to alleviate these problems, these remedies involve increased processing complexity and are generally very difficult to conduct in advanced technology.
Secondly, due to the reduced dimension of an inter-well STI, the tolerance for a misalignment during the photolithography process of forming the N-well and P-well is significantly reduced. Such a misalignment can easily cause a short between a P-well and an adjacent p+ region, and between an N-well and an adjacent n+ region, which may subsequently lead to a device malfunction and device failure. These and other drawbacks and processing difficulties cast great challenges on fitting a conventional STI in advanced technology.
On the other hand, the continuous scaling of device feature size in advanced technology has reached a point that suggests inter-well STI spacing of about the same as intra-well STI spacing, in order to reach the expected large circuit density on an IC and maintain the desired device performance.
One prior art STI embodiment aiming to address the device isolation needs in advanced technology includes a top portion having a straight sidewall and an enlarged bottom portion, as described in co-assigned, U.S. Pat. No. 5,915,192 to Liaw, et al, the disclosure of which is hereby incorporated for reference herein. However, during the process of forming this prior art STI structure, a significant amount of voids and seams are formed in the dielectric material which is filled into the opening of the STI. This leads to poor isolation characteristics, low STI yield and degradation of STI reliability.
Another prior art STI structure is described in “45-nm Node CMOS Integration with a Novel STI Structure and Full-NCS Interlayers for Low-Operation-Power (LOP) Applications” by M. Okuno, et al., Electron Devices Meeting, 2005. IEDM Technical Digest, IEEE International. The disclosure is hereby incorporated for reference. This simulated STI structure includes a locally oxidized STI bottom and a SiN liner (shown in FIG. 16 in said prior art) located between the STI filling material and the semiconductor substrate. The bottom portion, however, is not substantially enlarged to provide desirable isolation characteristics in advanced technology.
In view of these and other problems relating to a conventional STI and other prior art STI structures, there is a need for improved STI structures and method of forming in order to provide the desired STI isolation characteristics in advanced technology and, in the meantime, keep the manufacturing process cost-effective and robust in operation.